Convertidor Binario Hexadecimal

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Outputs assignment

-- y(6) <- a, y(5) <- b, y(4) <- c, y(3) <- d

-- y(2) <- e, y(1) <- f, y(0) <- g

entity decbcd7seg is

Port ( x : in STD_LOGIC_VECTOR (3 downto 0);

y : out STD_LOGIC_VECTOR (6 downto 0);

ena: out STD_LOGIC);

-- Define CLPD pinouts

attribute LOC : string;

attribute LOC of x : signal is "P124,P39,P94,P143"; -- SW1,SW0, BTN1, BTN0

attribute LOC of y : signal is "P56,P53,P60,P58,P57,P54,P61";

attribute LOC of ena: signal is "P126";

end decbcd7seg;

architecture Behavioral of decbcd7seg is

-- Using flow data modeling through WHEN-ELSE

-- The statements are not sequentially performed instead they

-- are concurrently performed.

begin

y <= "0000001" when x="0000" else -- 0

"1001111" when x="0001" else -- 1

"0010010" when x="0010" else -- 2

"0000110" when x="0011" else -- 3

"1001100" when x="0100" else -- 4

"0100100" when x="0101" else -- 5

"0100000" when x="0110" else -- 6

"0001111" when x="0111" else -- 7

"0000000" when x="1000" else -- 8

"0000100" when x="1001" else -- 9

"0001000" when x="1001" else -- a

"1100000" when x="1010" else -- b

"0110001" when x="1011" else -- c

"1000001" when x="1100" else -- d

"0110000" when x="1101"

...