Diseño De Temporizador
Enviado por f4b1t0 • 16 de Marzo de 2015 • 208 Palabras (1 Páginas) • 172 Visitas
Info: tco from clock "clk" to destination pin "display1[4]" through register "seg2_2[2]" is 9.756 ns
Info: + Longest clock path from clock "clk" to source register is 2.869 ns
Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 15; COMB Node = 'clk~clkctrl'
Info: 3: + IC(1.003 ns) + CELL(0.602 ns) = 2.869 ns; Loc. = LCFF_X8_Y13_N3; Fanout = 14; REG Node = 'seg2_2[2]'
Info: Total cell delay = 1.628 ns ( 56.74 % )
Info: Total interconnect delay = 1.241 ns ( 43.26 % )
Info: + Micro clock to output delay of source is 0.277 ns
Info: + Longest register to pin delay is 6.610 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y13_N3; Fanout = 14; REG Node = 'seg2_2[2]'
Info: 2: + IC(1.254 ns) + CELL(0.545 ns) = 1.799 ns; Loc. = LCCOMB_X4_Y13_N10; Fanout = 1; COMB Node = 'display1~42'
Info: 3: + IC(1.795 ns) + CELL(3.016 ns) = 6.610 ns; Loc. = PIN_AA5; Fanout = 0; PIN Node = 'display1[4]'
Info: Total cell delay = 3.561 ns ( 53.87 % )
Info: Total interconnect delay = 3.049 ns ( 46.13 % )
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