Programacion VHL
Enviado por FROILAN PEDRAZA MELCHOR • 19 de Noviembre de 2023 • Prácticas o problemas • 2.244 Palabras (9 Páginas) • 37 Visitas
library IEEE;
use IEEE.std_logic_1164.all;
entity fsm_cont_07 is
port(
CLK,RST: in std_logic;
st:in std_logic;
Q: out std_logic_vector(2 downto 0)
);
end fsm_cont_07;
architecture algoritmo of fsm_cont_07 is
signal Qp: std_logic_vector(2 downto 0) ;
signal Qn:std_logic_vector (2 downto 0);
begin
combinacional: process (st,Qp)
begin
case Qp is
when "000"=> --estado ceroS0
if(st='1') then
Qn<="001";
else
Qn<=Qp;
end if;
Q<="000";
when "001"=> --estado ceroS1
if(st='1') then
Qn<="010";
else
Qn<=Qp;
end if;
Q<="001";
when "010"=> --estado ceroS2
if(st='1') then
Qn<="011";
else
Qn<=Qp;
end if;
Q<="010";
when "011"=> --estado ceroS3
if(st='1') then
Qn<="100";
else
Qn<=Qp;
end if;
Q<="011";
...