Problema 1 library ieee
Enviado por tonivi35ca • 10 de Abril de 2023 • Tareas • 42.919 Palabras (172 Páginas) • 101 Visitas
Problema 1
library ieee;
use ieee.std_logic_1164.all;
entity multiplicador is
port( a,b:in std_logic_vector(2 downto 0);
salida:out std_logic;)
end multiplicador;
architecture behavioral of multiplicador is
begin
salida<=a*b;
Problema 2
library ieee;
use ieee.std_logic_1164.all;
entity rom is
port( oe:in std_logic;
addr:in std_logic_vector(3 downto 0);
salida:out std_logic_vector(7 downto 0));
end entity;
architecture data_flow of rom is
type rom is array (0 to 15) of std_logic_vector(7 downto 0);
constant memoria:rom:=(X"00",X"01",X"02",...,X"OF");
begin
salida<=memoria(conv_integer(addr)) when oe='0' else
others=>'Z';
end data_flow
Problema 3
library ieee;
use iee.std_logic_1164.all;
entity comparador if
generic(n:integer range 3 to 63:=10);
port( a,b:in std_logic_vector( 7 downto 0);
ce:in std_logic; --habilitacion
ab,a_b,ba:out std_logic;
end comparador;
architecture data_flow of comparador if
signal tmp:std_logic_vector(n downto 0);
begin
tmp<= "001" when a>b and ce="1" else
"010" when a=b and ce="1" else
"100";
ab<=tmp(0);
a_b<=tmp(1);
ba<=tmp(2);
end data_flow;
---------------------------------------------
library ieee;
use iee.std_logic_1164.all;
entity comparador if
generic(n:integer range 3 to 63:=10);
port( a,b:in std_logic_vector( 7 downto 0);
ce:in std_logic; --habilitacion ce=clk enable
clk:in std_logic;
ab,a_b,ba:out std_logic;
end comparador;
architecture behavioral of comparador is
signal tmp:std_logic_vector(2 downto 0);
begin
process(clk,a,b,ce)
begin
if reset='0' then
tmp<="000";
elsif clk='1' and clk'event then
if ce='1' then
if a<b then
tmp<="001";
elsif a=b then
tmp<="010";
else tmp<="100";
end if;
end if;
end if;
end process;
ab<=tmp(0);
a_b<=tmp(1);
ba<=tmp(2);
end behavioral;
Problema 4
COMBINACIONAL
library ieee
use ieee.std_logic_1164.all;
entity one_hot is
port( bcd:in std_logic_vector(3 downto 0);
clk: in std_logic;
reset: in std_logic;
error: out std_logic;
salida: out std_logic_vector( 9 downto 0);
end one_hot;
architecture behavioral of one_hot is
begin
salida<= "0000000001" when bcd="0000" else
"0000000010" when bcd="0001" else
"0000000100" when bcd="0010" else
"0000001000" when bcd="0011" else
"0000010000" when bcd="0100" else
"0000100000" when bcd="0101" else
"0001000000" when bcd="0110" else
"0010000000" when bcd="0111" else
"0100000000" when bcd="1000" else
"1000000000" when bcd="1001" else
"0000000000;
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SECUENCIAL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity one_hot is
Port ( BCD : in std_logic_vector(3 downto 0);
clk : in std_logic;
reset : in std_logic;
error : out std_logic;
salida : out std_logic_vector(9 downto 0));
end one_hot;
architecture Behavioral of one_hot is
begin
process(clk,reset,bcd)
begin
if ( reset = '1') then
salida <= "0000000000"; error <= '1';
elsif ( clk'event and clk ='1') then
case bcd is
when "0000" => salida <= "0000000001"; error <= '0';
when "0001" => salida <= "0000000010"; error <= '0';
when "0010" => salida <= "0000000100"; error <= '0';
when "0011" => salida <= "0000001000"; error <= '0';
when "0100" => salida <= "0000010000"; error <= '0';
when "0101" => salida <= "0000100000"; error <= '0';
when "0110" => salida <= "0001000000"; error <= '0';
when "0111" => salida <= "0010000000"; error <= '0';
when "1000" => salida <= "0100000000"; error <= '0';
when "1001" => salida <= "1000000000"; error <= '0';
when others => salida <= "0000000000"; error <= '1';
end case;
end if;
end process;
end Behavioral
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entity deco is
Port ( entrada : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
...