Análisis en pequeña señal

[pic 1]

ANALISIS EN PEQUEÑA SEÑAL

Tarea 4

[pic 2]

Objetivo: Realizar el análisis en pequeña señal del siguiente circuito de transistores y comprobar los cálculos sustituyendo los valores obtenidos en la simulación en Tanner EDA

Desarrollo teórico 
        Análisis SS de la ganancia de voltaje

[pic 3][pic 4]

𝑉𝑎 (𝑔𝑑𝑠2 + 𝑔𝑑𝑠3) − 𝑉𝑜 (𝑔𝑑𝑠2) = −𝑉𝑖𝑛𝑔𝑚2 + 𝑉𝑜 𝑔𝑚2

𝑉𝑎 (𝑔𝑑𝑠2 + 𝑔𝑑𝑠3) − 𝑉𝑜 (𝑔𝑑𝑠2 + 𝑔𝑚2) = −𝑉𝑖𝑛𝑔𝑚2

[pic 5]

𝑉𝑜 (𝑔𝑑𝑠1 + 𝑔𝑑𝑠2) − 𝑉𝑎 (𝑔𝑑𝑠2) = 𝑉𝑖𝑛𝑔𝑚2 − 𝑉𝑜𝑔𝑚2

𝑉𝑜 (𝑔𝑑𝑠1 + 𝑔𝑑𝑠2 + 𝑔𝑚2) − 𝑉𝑎 (𝑔𝑑𝑠2) = 𝑉𝑖𝑛𝑔𝑚2

[pic 6]

[pic 7]

𝑉𝑜 (𝑔𝑑𝑠1𝑔𝑑𝑠2 + 𝑔𝑑𝑠1𝑔𝑑𝑠3 + 𝑔𝑑𝑠2𝑔𝑑𝑠2 + 𝑔𝑑𝑠2𝑔𝑑𝑠3 + 𝑔𝑚2𝑔𝑑𝑠2 + 𝑔𝑚2𝑔𝑑𝑠3 − 𝑔𝑑𝑠2𝑔𝑑𝑠2 − 𝑔𝑚2𝑔𝑑𝑠2) = 𝑉𝑖𝑛 (𝑔𝑑𝑠2𝑔𝑚2 + 𝑔𝑑𝑠3𝑔𝑚2 − 𝑔𝑚2𝑔𝑑𝑠2)

𝑉𝑜 (𝑔𝑚2𝑔𝑑𝑠3) = 𝑉𝑖𝑛 (𝑔𝑑𝑠3𝑔𝑚2)

[pic 8]

 Análisis SS la impedancia de salida

[pic 9][pic 10]

𝑉𝑎 (𝑔𝑑𝑠2 + 𝑔𝑑𝑠3) − 𝑉𝑜 (𝑔𝑑𝑠2) = 𝑉𝑜𝑔𝑚2

𝑉𝑎 (𝑔𝑑𝑠2 + 𝑔𝑑𝑠3) = 𝑉𝑜 (𝑔𝑑𝑠2 + 𝑔𝑚2)

[pic 11]

𝑉𝑜 (𝑔𝑑𝑠1 + 𝑔𝑑𝑠2) − 𝑉𝑎 (𝑔𝑑𝑠2) = 𝐼o− 𝑉𝑜𝑔𝑚2

𝑉𝑜 (𝑔𝑑𝑠1 + 𝑔𝑑𝑠2 + 𝑔𝑚2) − 𝑉𝑎 (𝑔𝑑𝑠2) = 𝐼o

=Io[pic 12]

 =Io[pic 13]

[pic 14]

[pic 15]

[pic 16]

Esquemático

Ganancia

[pic 17]

Impedancia

[pic 18]

Código de programa

Ganancia

* SPICE export by:  S-Edit 16.01

* Export time:      Tue Apr 26 17:49:08 2022

* Design:           pequenasenal

* Cell:             ZO

* Interface:        view0

* View:             view0

* View type:        connectivity

* Export as:        top-level cell

* Export mode:      hierarchical

* Exclude empty cells: yes

* Exclude .model:   no

* Exclude .end:     no

* Exclude simulator commands:     no

* Expand paths:     yes

* Wrap lines:       no

* Root path:        C:\Users\PC\Documents\documentos tanner\pequenasenal

* Exclude global pins:   no

* Exclude instance locations: no

* Control property name(s): SPICE

********* Simulation Settings - General Section *********

.probe

.option probev

.option probei

.option probeq

.include "C:\Program Files\Tanner EDA\AMI_050\TechSetups\typical.sp"

***** Top Level *****

CC1 Vo Gnd  1p $ $x=1200 $y=1000 $w=600 $h=400

MNMOS_1 N_1 N_4 Vss Vss CMOSN W=2.7u L=900n AS=2.43p PS=7.2u AD=2.43p PD=7.2u $ $x=100 $y=-300 $w=400 $h=600

MPMOS_1 N_1 N_2 Vo Vo CMOSP W=16.2u L=900n AS=14.58p PS=34.2u AD=14.58p PD=34.2u $ $x=100 $y=600 $w=400 $h=600

MPMOS_2 Vo N_3 Vdd Vdd CMOSP W=1.5u L=900n AS=1.35p PS=4.8u AD=1.35p PD=4.8u $ $x=100 $y=1500 $w=400 $h=600

VV4 N_3 Gnd  DC 55m $ $x=-400 $y=1500 $w=600 $h=400 $r=90

VV5 Gnd N_4  DC 1.1684 $ $x=-400 $y=-300 $w=600 $h=400 $r=270

VVD Vdd Gnd  DC 2.5 $ $x=-2400 $y=1300 $w=400 $h=600

VVS Gnd Vss  DC 2.5 $ $x=-2400 $y=500 $w=400 $h=600

VV2 N_2 Gnd  DC -1.1684 AC 1 0 $ $x=-1000 $y=300 $w=400 $h=600

********* Simulation Settings - Analysis Section *********

.op

.ac dec 20 1 100e6

********* Simulation Settings - Additional SPICE Commands *********

.end

Impedancia

* SPICE export by:  S-Edit 16.01

* Export time:      Tue Apr 26 17:28:28 2022

* Design:           pequenasenal

* Cell:             ZO

* Interface:        view0

* View:             view0

* View type:        connectivity

* Export as:        top-level cell

* Export mode:      hierarchical

* Exclude empty cells: yes

* Exclude .model:   no

* Exclude .end:     no

* Exclude simulator commands:     no

* Expand paths:     yes

* Wrap lines:       no

* Root path:        C:\Users\PC\Documents\documentos tanner\pequenasenal

* Exclude global pins:   no

* Exclude instance locations: no

* Control property name(s): SPICE

...